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[ak4160] ms1313-e-01 2011/11 - 1 - general description the ak4160 is a low operating voltage and low power consumption 16-channel c apacitive touch sensor. maximum 8 channels out of the 16-channel can be c onfigured to led drive or gpio. the ak4160 has a channel independent automatic correct function of environmental drifts for each sense input. it reduces false detection by continuous calibrati on of the internal reference val ue in the situation when the input capacitance of the touch switch is changed by the external fa ctors such as hydrothermal conditions. the automatic initial setting function sets the charge current and charge time according to the size and the shape of a touch switch. the ak4160 c an be configured via serial interfac es, it is suitable for mobile phones, pcs and home electric applications. feature ? up to 16 capacitive sensor inputs ? up to 8 general purpose inputs/outputs with pwm control for led ? automatic initial setting function for the charge current and time ? independent automatic environmental drifts correct function for each sense terminal ? independent threshold configuration for each sense terminal ? selectable multi touch feature ? integrated median averaging filter ? selectable 3 interrupt outputs that be able to use as gpios ? reset input pin ? i 2 c serial interface ? 10 bit sar a/d converte r with s/h circuit ? integrated regulator ? low power consumption: typ. 3.4ua (sampling rate=512ms, 16ch sensor input active) ? power down current: typ. 1.0ua ? low power operation: vdd = 1.71v ~ 3.6v ? operating temperature: ta = -40 ~ 85 c ? package: 28pin qfn (4.0mm x 4.0mm, pitch 0.4mm) i 2 c-bus is a trademark of nxp b.v. ak4160 16-channel capacitive touch sensor ic
[ak4160] ms1313-e-01 2011/11 - 2 - sar adc vdd power control scl rstn rref vss vreg sda ad0 ad1 serial interface clock irq output irq0n / gpioa control & register current sources auto calibration led driver pwm logic gpio logic data filter cs0 irq1n / gpiob irq2n / gpioc cs1 cs2 cs3 cs4 cs5 cs6 cs7 cs8 / gpio7 cs9 / gpio6 cs10 / gpio5 cs11 / gpio4 cs12 / gpio3 cs13 / gpio2 cs14 / gpio1 cs15 / gpio0 switch matrix figure 1. block diagram ordering guide ak4160en ? 40 +85 c 28pin qfn (4mm x 4mm, 0.4mm pitch) AKD4160 ak4160en evaluation board
[ak4160] ms1313-e-01 2011/11 - 3 - pin layout 21 20 19 18 17 16 15 14 13 12 11 10 9 8 1 2 3 4 5 6 7 cs11 / gpio4 irq0n / gpioa irq1n / gpiob irq2n / gpioc ad0 scl ad1 sda cs10 / gpio5 cs12 / gpio3 cs13 / gpio2 cs15 / gpio0 cs14 / gpio1 vdd rstn vreg vss rref cs0 cs1 cs2 cs9 / gpio6 cs8 / gpio7 cs7 cs6 cs5 cs4 cs3 22 23 24 25 26 27 28 ak4160en top view
[ak4160] ms1313-e-01 2011/11 - 4 - pin/function pin no. pin name type ( note 1 ) i/o ( note 2 ) function reset state rstn pin = ?l? 1 irq0n / gpioa d i/o interrupt b it0 / gpio pina hi-z (input) 2 irq1n / gpiob d i/o interrupt b it1 / gpio pinb hi-z (input) 3 irq2n / gpioc d i/o interrupt b it2 / gpio pinc hi-z (input) 4 ad0 d i i 2 c slave address bit 0 - 5 scl d i i 2 c serial clock input - 6 ad1 d i i 2 c slave address bit 1 - 7 sda d i/o i 2 c serial data input/ output hi-z (input) 8 rstn d i reset pin internal pull-up by 100k ? (typ) - 9 vreg d o internal regulator output current must not be taken from this pin. a 47nf 20% capacitor should be connected between this pin and vss. output 10 vss gnd - ground - 11 rref a i reference resistor input a 100k ? 1% resistor should be connected between this pin and vss. hi-z (open) 12 cs0 a i/o cap sense pin0 l 13 cs1 a i/o cap sense pin1 l 14 cs2 a i/o cap sense pin2 l 15 cs3 a i/o cap sense pin3 l 16 cs4 a i/o cap sense pin4 l 17 cs5 a i/o cap sense pin5 l 18 cs6 a i/o cap sense pin6 l 19 cs7 a i/o cap sense pin7 hi-z (open) ( note 5 ) 20 cs8 / gpio7 a/d i/o cap sense pin8 / gpio pin7 hi-z (input) 21 cs9 / gpio6 a/d i/o cap sense pin9 / gpio pin6 hi-z (input) 22 cs10 / gpio5 a/d i/o cap sense pin10 / gpio pin5 hi-z (input) 23 cs11 / gpio4 a/d i/o cap sense pin11 / gpio pin4 hi-z (input) 24 cs12 / gpio3 a/d i/o cap sense pin12 / gpio pin3 hi-z (input) 25 cs13 / gpio2 a/d i/o cap sense pin13 / gpio pin2 hi-z (input) 26 cs14 / gpio1 a/d i/o cap sense pin14 / gpio pin1 hi-z (input) 27 cs15 / gpio0 a/d i/o cap sense pin15 / gpio pin0 hi-z (input) 28 vdd pwr - power supply : 1.71v ~ 3.6v - note 1. a (analog terminal), d (digita l terminal), gnd (ground), pwr (power) note 2. i (input terminal), o (output terminal) note 3. all digital input pins ( ad0, ad1, scl, sda) must not be allowed to float. note 4. when gpio pins (gpioa ~ gpioc, gpio0 ~ gpio7) are configured to digital inputs without internal pull resistor, the pins must not be left floating. note 5. outputs ?l? after releasing a reset. handling of unused pins the unused i/o pins must be connected appropriately. classification pin name setting digital irq0n / gpioa ~ irq2n / gpioc this pin must be configured with internal pull-up/down resistor or be connected to vss or vdd. analog cs0 ~ cs7 this pin must be open. analog/digital cs8 / gpio7 ~ cs15 / gpio0 this pin must be configured with internal pull-down resistor or be connected to vss.
[ak4160] ms1313-e-01 2011/11 - 5 - absolute maximum ratings (vss = 0v ( note 6 )) parameter symbol min max unit power supply vdd -0.3 4.3 v input current any pins except for supply iin - 10 ma gpio source current per pin isource - 12 ma gpio sink current per pin isink - 1.2 ma input voltage ( note 7 ) vin -0.3 vdd+0.3 or 4.3 v ambient temperature (power applied) ta -40 85 c storage temperature tstg -65 150 c note 6. all voltages with respect to ground. note 7. for all input pins. the maximum value is smaller value between (vdd+0.3)v and 4.3v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommend operating conditions (vss = 0v ( note 6 )) parameter symbol min typ max unit power supply vdd 1.71 1.8 3.6 v note 6. all voltages with respect to ground. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4160] ms1313-e-01 2011/11 - 6 - analog characteristics (ta = -40 c ~ 85 c, vdd = 1.8v; unless otherwise specified) parameter symbol min typ max unit a/d converter resolution reso - 10 - bits touch sensor charge current variation against nominal value ( note 8 ) ichg -5 - 5 % power supply current measurement current (all function in active) imeas - 0.8 1 ma idle current iidle - 3 11 ua average supply current tsr= 4ms, nch=16, tchg=2us, nf1s=4 tsr= 8ms, nch=16, tchg=2us, nf1s=4 tsr= 16ms, nch=16, tchg=2us, nf1s=4 tsr= 32ms, nch=16, tchg=2us, nf1s=4 tsr= 64ms, nch=16, tchg=2us, nf1s=4 tsr=128ms, nch=16, tchg=2us, nf1s=4 tsr=256ms, nch=16, tchg=2us, nf1s=4 tsr=512ms, nch=16, tchg=2us, nf1s=4 idd - - - - - - - - 54 29 16 9 6 5 4 3.4 - - - - - - - - ua ua ua ua ua ua ua ua shutdown current nch=0 (shutdown mode) ishut - 1 9 ua note 8. sense terminal voltage condition: the ad conversion value should be less or equal to vdd-0.2[v]. the charge current is dependent on the operating voltage, and is configured with registers in ?0.556 x vdd [ua]? to ?35.028 x vdd [ua]? range. dc characteristics (logic i/o) (ta = -40 c ~ 85 c, vdd = 1.71v ~ 3.6v; unless otherwise specified) parameter symbol min typ max unit input leakage current ( note 9 ) ( note 10 ) iilh -1.0 - 1.0 ua input high voltage vih 0.7xvdd - - v input low voltage vil - - 0.3xvdd v output high voltage ( note 11 ) ( note 14 ) io=-10ma vohf1 vdd-0.5 - - v output high voltage ( note 11 ) ( note 15 ) io=-3.3ma voh1 vdd-0.5 - - v output low voltage ( note 11 ) ( note 14 ) io=1ma volf1 - - 0.5 v output low voltage ( note 11 ) ( note 15 ) io=0.33ma vol1 - - 0.5 v output high voltage ( note 12 ) ( note 14 ) io=-6ma vohf2 vdd-0.5 - - v output high voltage ( note 12 ) ( note 15 ) io=-2ma voh2 vdd-0.5 - - v output low voltage ( note 12 ) ( note 14 ) io=6ma volf2 - - 0.5 v output low voltage ( note 12 ) ( note 15 ) io=2ma vol2 - - 0.5 v output low voltage ( note 13 ) io=3ma vol3 - - 0.5 v pull-up current ( note 11 ) ( note 12 ) (pull-up setting) ipu 5 - 200 ua pull-down current ( note 11 ) ( note 12 ) (pull-down setting) ipd -200 - -5 ua note 9. gpio0~gpio7, ad0, ad1, gpioa~gpioc, scl, sda note 10. except for the rstn pin. the rstn pin has an internal pull-up device, normally 100k ? . note 11. gpio0~gpio7 note 12. irq0n~irq2n note 13. sda note 14. full drive operation note 15. 1/3 drive operation
[ak4160] ms1313-e-01 2011/11 - 7 - switching characteristics (ta = -40 c ~ 85 c, vdd = 1.71v ~ 3.6v; unless otherwise specified) parameter symbol min typ max units touch sensor charge time ( note 16 ) tchg -15 - 15 % sampling rate ( note 17 ) tsr -35 - 35 % pwm frequency accuracy accf -35 - 35 % reset timing reset pulse width ( note 18 ) trstn 10 - - us reset pin pulse width of spike noise suppressed by input filter ( note 19 ) trstns 0.5 - - us start up timing power up time ( note 20 ) tpu - - 1 ms power up rise time tpr - - 20 ms power up interval time ( note 21 ) tpi 20 - - ms i 2 c scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 22 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s pulse width of spike noise suppressed by input filter tsp 50 - - ns capacitive load on bus cb - - 400 pf note 16. variation against nominal value of tchg (0.25us to 32us) note 17. variation against nominal value of tsr (4ms to 512ms) note 18. the ak4160 can be reset by the rstn pi n = ?l?. this is to initialize the ak4160 for sure. note 19. pulse width of spike noise supp ressed by input filter of the rstn pin. note 20. time as the starting point when reached vdd=1.71v and vreg=1.0v, with creg=47nf. note 21. the condition of ?vdd=vss? should be kept during the power up interval time. note 22. data must be held for sufficient time to bridge the 300ns transition time of scl. vil rstn trstn trstns figure 2. reset timing diagram
[ak4160] ms1313-e-01 2011/11 - 8 - tpu vdd 1.71v vreg i2ci/f 1.00v en able tpi 0.0 v tpr figure 3. power up timing diagram thigh scl sda vih tlow tbuf th d:sta tr tf thd:dat tsu:dat t su: sta stop st art st art stop tsu:sto vil vih vil tsp figure 4. i 2 c interface timing diagram
[ak4160] ms1313-e-01 2011/11 - 9 - operation overview operation of touch sensor the touch switch (capacitor) that is connected to the sense input is charged up with direct current during a given period of time. the switch is connected to ground before the measurement. as a result, the touch switch capacitance is completely discharged before start being charged. when the touch switch is fully charged, the voltage is inversely proportional to the capacitance. when the touch switch is touched, this charge voltage decreases because th e capacitance value when the switch is touched is larger than when not touched. the charge d voltage is converted to a digital data by adc. the data is get through the noise reduction filter, and compared to a to uch threshold value. when the measurement value exceeds the threshold that is corrected environmental drifts, the ak4160 updates the status register to the touch detected state. sar adc vdd vss environmental drifts correction second noise reduction filter first noise reduction filter vss touch switch control logic (touch de tection) figure 5. touch sensor block diagram capacitance ? voltage converter the touch switch (capacitance c), that is connected to the sens e terminal, is charged with a direct current i during the period t. the voltage of the sense terminal is v=(i t)/c, and if the values of i and t are constant, the charged voltage is inversely proportional to the value of ca pacitance c. the charge voltage is de creased by v=(i t)/(c+dc) when the capacitance c is increased by dc by touching the touch switch comparing with the not touched status. after the voltage is charged, the ak4160 discharges the sense terminal by a dir ect current i, during t period. at the same time, the adc converts the terminal value. the sense terminal must be co nnected to ground before the next measurement. the next measurement should be started when the se nse terminal is discharged completely. next measuremen t v t t charge discharge ground a/d conver t measurement value c t i v = dc c t i v + = (no t touched) (touched) figure 6. the voltage transaction of a sense terminal
[ak4160] ms1313-e-01 2011/11 - 10 - noise reduction filter the voltage of a sense terminal is measured for n consecutive times. then the first filter calculates the average value, discarding the minimum and the maximum values. the n of the measurement time is user-sel ectable from 4, 6, 10, and 18 times. (address 0x70 nf1s1-0 bits) the sampling rate is dependent on the charge time. the second filter has the same structure as the first filter. th e outputs of the first filter are input to the second filter. t he n of the measurement time is user-selectable from 4, 6, 10, and 18 times independent of the first filter. (address 0x70 nf2s1-0 bits) the sampling rate of the second filter is user-sel ectable from 4ms to 512ms in factorial of 2 steps. (address 0x74 tsr2-0 bits) the output rate of the second filter is ?sampling rate sample count?. the output data is compared to ?the noncontact reference value? that output by the calib ration circuit for environment changes. cs0 sampling rate result update calculation of median averaging after 6 measurement, repeating charge and discharge. (6 sample setting in the first filter) the voltage of sense terminal cs1 calculation of median averaging after 4 times acquisition of the output data from the first filter, and updating to result (4 sample setting in the second filter) cs0 data cs1 data figure 7. the measurement of a sense terminal and the data update
[ak4160] ms1313-e-01 2011/11 - 11 - correction of environment drifts the capacitance of a sense terminal is influenced from the hydrothermal condition and the grime of the surface. the ak4160 monitors the m easurement value continuously. if the value is changed by the environment, ?the noncontact reference value? is corrected. the reference value is char ged very slowly following the measurement value of not touched status by the correction circuit. the threshold of touch detection and release detection is synchronized with the reference value. in case of the touch detection, the refe rence value is not followed to the measurement value. the increasing rate and the decreasing rate of the referen ce value can be configured independently. when a finger approaches slowly to the touch switch, the measurement value is decreased gradua lly. the decreasing rate of the reference value must be configured slower than the increasing rate to avoid false detection. touch threshould v t touch release threshould reference value measurement value v t reference value measurement value release threshould touch threshould environmental drift figure 8. the voltage of sense terminal and automatic correction of environmental drift the initial reference value after the reset release can be selected from a user configuration and the automatic configuration that configured to 32/32, 31/32, and 30/32 of the first measurement value. (address 0x70 rim1-0 bits) debounce the touch status is updated when the output of the second f ilter is judged as touched or released for n times continuously for a stabilized touch detection. the count ?n? is user-selectable from 0 to 15 times. (address 0x71 debt3-0, debr3-0 bits) the update rate of the touch status is calculated as follows. ?sampling rate of second filter x sample count of second filter x debounce count? automatic initial setting the capacitance of a sensor is different according to the si ze and the shape of a touch switc h. the charge current and the charge period should be configured adequately for optim al sensitivity to every touch switches. (address 0x45-0x54 ccn5-0 bits, address 0x55-0x5c ctn2-0 bits) the ak4160 has the automatic initial calibration that configured to the optimal setting. (address 0x5f acc) external reset the rstn pin is input terminal for a lo w-active asynchronous reset with an in ternal pull-up resistor. a measurement operation is aborted and the internal circuit is initialized immedi ately by the reset. the serial interface transaction is also aborted. if the reset is executed in a transaction, an unint ended access may occur. therefore, the reset must be executed without transaction of serial interface.
[ak4160] ms1313-e-01 2011/11 - 12 - programmable interrupt a state change of a sense terminal or gpio is notified to the host by the irq output. the output driver is selectable from open-drain type and totem-pole type, and the activate polarity can be configured. the active condition of the irq pins is user-selectable as follows. 1. state change 2. touch (state change from release stat e to touch state at sense terminals) 3. release (state change from touch state to release state at sense terminals) 4. measurement execution (any states) 5. input edge detection of gpio three irq pins can be independently configured to different conditions. several user applications can be supported by the flexible configuration. the unused pin of irq pins can simply be configured as a gpio pin. multi touch the ak4160 supports multi touch operation. the multi touch function can be controlled, improving operability of an application by enabling and disabling. multi touch enabled the status register reflects a touch detection of each sense term inal directly. update of the status register is independent for each sense terminal. the state of a sense terminal is not influenced by the state of other sense terminals. multi touch disabled update of the status register is executed singularly. this is for an application that expect s a single touch. the user can select a mode shown below. 1. release all in this mode, if some sense terminals are touched while all sense terminals are internally released, only the most pushed sense terminal is detected as touched and other touched sense terminal statuses are not updated to touched. (their statuses remain as released, but internally they are judged as touched.) all sense terminals must be released internally, for a new touch detection in this state. 2. release ch in this mode, if some sense terminals are touched while all sense terminals are internally released, only the most pushed sense terminal is detected as touched and other touched sense terminal statuses are not updated to touched. (their statuses remain as released, but internally they are judged as touched.) the most pushed sense terminal must be released internally, for a new touch detection in this state. when the most pushed sense terminal is released, the status of second most pushed sense terminal is updated to touched. this exclusive update (multi touch disabled) can independen tly be assigned to each sense terminal. however, release all or release ch mode configuration is common to all sense terminals which are assigned as multi touch disabled. ?the most pushed sense terminal? means a sense terminal which has the biggest difference between measured and reference values. if there was a tie for the biggest difference va lue, the state of the sense terminal which has the smallest channel number will be changed. by the user setting, ?a touched sense terminal with the smallest channel number? can be chosen as the condition of release ch mode instead of the ?the most pushed terminal?.
[ak4160] ms1313-e-01 2011/11 - 13 - gpio 8 out of 16 channels can be allocated to gpio. in or output modes of gpio is selected by the user. ? input mode 1. connect a pull-up or pull-down resistor. 2. debounce function (update only for continuous inputs of n times) 3. irq interrupt permitted or not permitted 4. irq interrupt edge select (? ? or ? ?) the ak4160 monitors terminal level in every 31.25us by the debounce function. when the in put levels are the same for selected number of times continuously, the ak4160 reflects it as an input value. setting value continuous number of times continuous time (ms) 0 1 - 1 4 0.125 2 8 0.25 3 16 0.5 4 32 1 5 64 2 6 128 4 7 256 8 8 512 16 9 1024 32 10 2048 64 11 4096 128 12 8192 256 13 16384 512 14,15 32768 1024 table 1. debounce function setting ? output mode 1. selected from cmos, open drain (?h? or ?l?) outputs 2. drive ability select 3. user setting output or chn status output from the gpion pin. 4. pwm function brightness adjustment of leds can be made by pwm function. 125, 250, 500hz or 1khz can be configured independently for each gpio pin. the duty ratio can be set in 32 levels (5bit). when driving led, high-side output should be selected to decrease influences to the measuring result.
[ak4160] ms1313-e-01 2011/11 - 14 - digital i/f the ak4160 is controlled by a microprocessor via i 2 c bus supporting standard mode (100khz) and fast mode (400khz). note that the ak4160 operates in those two modes and does not support a high speed mode i 2 c-bus system (3.4mhz). the ak4160 can operate as a slave device on the i 2 c bus network. the digital i/o of ak4160 operates off of supply voltage down to 1.71v in order to connect a low voltage microprocessor. micro- processor ( p ) i 2 c bus controller ak4160 scl sda touch switch irq0n/irq1n/irq2n rp rp vdd=1.71v ~ 3.6v ad0,ad1 ?l? or ?h? figure 9. digital i/f 1. write operations figure 10 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 14 ). after the start condition, a slave address is sent. this addr ess is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant five bits of the slav e address are fixed as ?10100?. the next bits is ad1 and ad0 (device address bit). these bits identify the specific device on the bus. the hard-wired input pin (ad0, ad1 pin) set this device address bit ( figure 11 ). if the slave address matches that of the ak4160, the ak4160 generates an acknowledge and the operation is executed. the master must generate the acknowledge-relate d clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 15 ). r/w bit value of ?1? indicates that th e read operation is to be executed. ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4160. the format is msb first, and those most significant two bits are fixed to zeros ( figure 12 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 13 ). the ak4160 generates an acknowledge after each byte is received. a data transfer is always terminated by stop condition generated by the master. a lo w to high transition on the sda line while scl is high defines stop condition ( figure 14 ). the ak4160 can perform more than one by te write operation per sequence. after receipt of the thir d byte the ak4160 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 6-bit address counter is incremented by one, and the next data is automatically taken in to the next address. if the address exceeds ?9fh? prior to generating stop condition, the address counter will ?roll ove r? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only change when the clock signal on the scl line is low ( figure 16 ) except for the start and stop conditions.
[ak4160] ms1313-e-01 2011/11 - 15 - sda s t a r t ak41 60 ack s sla ve a ddress data (n) p s t o p r/w= ?0? su b a ddress(n) ak416 0 ack ak41 60 ack ak416 0 ack data (n+1) data (n+ x ) ak4160 ack ak41 60 ack figure 10. data transfer sequence at the i 2 c-bus mode 1 0 1 0 0 ad1 ad0 r/w (ad0 and ad1 should match with ad0 and ad1 pin.) figure 11. the first byte a7 a6 a5 a4 a3 a2 a1 a0 figure 12. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 13. byte structure after the second byte scl sda stop condition start condition s p figure 14. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 15. acknowledge on the i 2 c-bus
[ak4160] ms1313-e-01 2011/11 - 16 - scl sda data line stable; data valid change of data allowed figure 16. bit transfer on the i 2 c-bus 2. read operations set the r/w bit = ?1? for the re ad operation of the ak4160. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle after the recei pt of the first data word. after receiv ing each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds ?9fh? prior to generating stop condi tion, the address counter will ?roll over ? to 00h and the data of 00h will be read out. the register read ope ration allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after th e register address is acknowledged, the master immediately reissues the start re quest and the slave address with the r/w bit ?1?. the ak4160 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates stop condition in stead, the ak4160 ceases transmission. sda s t a r t ak416 0 ack s slave a dd ress data (n) p s t o p r/w= ?1? data (n+1) data (n+x) mast r ack mastr ack mast r ack mast r nack ak4160 ac k s slave a ddress r/w = ?0? ak4160 ack sub a ddr ess(n ) s t a r t figure 17. register address read
[ak4160] ms1313-e-01 2011/11 - 17 - register map register description type symbol fields initial address d7 d6 d5 d4 d3 d2 d1 d0 value 0x00 touch status r ts ts[15] ts[14] ts[13] ts[12] ts[11] ts[10] ts[9] ts[8] 0x00 0x01 r ts[7] ts[6] ts[5] ts[4] ts[3] ts[2] ts[1] ts[0] 0x00 0x02 irq status r irqs drdy touch rel acf range gpin reserved reserved 0x00 0x03 w/r iover reserved reserved reserved reserved irq2 irq1 irq0 0x00 0x04 gpio input data r gpin gpin[7] gpin[6] gpin [5] gpin[4] gpin[3] gpin [2] gpin[1] gpin[0] 0x00 0x05 cs0 data register r csd0 csd0[15] csd0[14] csd0[13] csd0[12] csd0[11] csd0[10] csd0[9] csd0[8] 0x00 0x06 r csd0[7] csd0[6] csd0[5] csd0[4] csd0[3] csd0[2] csd0[1] csd0[0] 0x00 0x07 cs1 data register r csd1 csd1[15] csd1[14] csd1[13] csd1[12] csd1[11] csd1[10] csd1[9] csd1[8] 0x00 0x08 r csd1[7] csd1[6] csd1[5] csd1[4] csd1[3] csd1[2] csd1[1] csd1[0] 0x00 0x09 cs2 data register r csd2 csd2[15] csd2[14] csd2[13] csd2[12] csd2[11] csd2[10] csd2[9] csd2[8] 0x00 0x0a r csd2[7] csd2[6] csd2[5] csd2[4] csd2[3] csd2[2] csd2[1] csd2[0] 0x00 0x0b cs3 data register r csd3 csd3[15] csd3[14] csd3[13] csd3[12] csd3[11] csd3[10] csd3[9] csd3[8] 0x00 0x0c r csd3[7] csd3[6] csd3[5] csd3[4] csd3[3] csd3[2] csd3[1] csd3[0] 0x00 0x0d cs4 data register r csd4 csd4[15] csd4[14] csd4[13] csd4[12] csd4[11] csd4[10] csd4[9] csd4[8] 0x00 0x0e r csd4[7] csd4[6] csd4[5] csd4[4] csd4[3] csd4[2] csd4[1] csd4[0] 0x00 0x0f cs5 data register r csd5 csd5[15] csd5[14] csd5[13] csd5[12] csd5[11] csd5[10] csd5[9] csd5[8] 0x00 0x10 r csd5[7] csd5[6] csd5[5] csd5[4] csd5[3] csd5[2] csd5[1] csd5[0] 0x00 0x11 cs6 data register r csd6 csd6[15] csd6[14] csd6[13] csd6[12] csd6[11] csd6[10] csd6[9] csd6[8] 0x00 0x12 r csd6[7] csd6[6] csd6[5] csd6[4] csd6[3] csd6[2] csd6[1] csd6[0] 0x00 0x13 cs7 data register r csd7 csd7[15] csd7[14] csd7[13] csd7[12] csd7[11] csd7[10] csd7[9] csd7[8] 0x00 0x14 r csd7[7] csd7[6] csd7[5] csd7[4] csd7[3] csd7[2] csd7[1] csd7[0] 0x00 0x15 cs8 data register r csd8 csd8[15] csd8[14] csd8[13] csd8[12] csd8[11] csd8[10] csd8[9] csd8[8] 0x00 0x16 r csd8[7] csd8[6] csd8[5] csd8[4] csd8[3] csd8[2] csd8[1] csd8[0] 0x00 0x17 cs9 data register r csd9 csd9[15] csd9[14] csd9[13] csd9[12] csd9[11] csd9[10] csd9[9] csd9[8] 0x00 0x18 r csd9[7] csd9[6] csd9[5] csd9[4] csd9[3] csd9[2] csd9[1] csd9[0] 0x00 0x19 cs10 data register r csd10 csd10[15] csd10[14] csd10[13] csd10[12] csd10[11] csd10[10] csd10[9] csd10[8] 0x00 0x1a r csd10[7] csd10[6] csd10[5] csd10[4] csd10[3] csd10[2] csd10[1] csd10[0] 0x00 0x1b cs11 data register r csd11 csd11[15] csd11[14] csd11[13] csd11[12] csd11[11] csd11[10] csd11[9] csd11[8] 0x00 0x1c r csd11[7] csd11[6] csd11[5] csd11[4] csd11[3] csd11[2] csd11[1] csd11[0] 0x00 0x1d cs12 data register r csd12 csd12[15] csd12[14] csd12[13] csd12[12] csd12[11] csd12[10] csd12[9] csd12[8] 0x00 0x1e r csd12[7] csd12[6] csd12[5] csd12[4] csd12[3] csd12[2] csd12[1] csd12[0] 0x00 0x1f cs13 data register r csd13 csd13[15] csd13[14] csd13[13] csd13[12] csd13[11] csd13[10] csd13[9] csd13[8] 0x00 0x20 r csd13[7] csd13[6] csd13[5] csd13[4] csd13[3] csd13[2] csd13[1] csd13[0] 0x00 0x21 cs14 data register r csd14 csd14[15] csd14[14] csd14[13] csd14[12] csd14[11] csd14[10] csd14[9] csd14[8] 0x00 0x22 r csd14[7] csd14[6] csd14[5] csd14[4] csd14[3] csd14[2] csd14[1] csd14[0] 0x00 0x23 cs15 data register r csd15 csd15[15] csd15[14] csd15[13] csd15[12] csd15[11] csd15[10] csd15[9] csd15[8] 0x00 0x24 r csd15[7] csd15[6] csd15[5] csd15[4] csd15[3] csd15[2] csd15[1] csd15[0] 0x00 0x25 cs0 touch threshold w/r tt0 t8x0 tt0[6] tt0[5] tt0[4] tt0[3] tt0[2] tt0[1] tt0[0] 0x00 0x26 cs0 release threshold w/r rt0 r8x0 rt0[6] rt0[5] rt0[4] rt0[3] rt0[2] rt0[1] rt0[0] 0x00 0x27 cs1 touch threshold w/r tt1 t8x1 tt1[6] tt1[5] tt1[4] tt1[3] tt1[2] tt1[1] tt1[0] 0x00 0x28 cs1 release threshold w/r rt1 r8x1 rt1[6] rt1[5] rt1[4] rt1[3] rt1[2] rt1[1] rt1[0] 0x00 0x29 cs2 touch threshold w/r tt2 t8x2 tt2[6] tt2[5] tt2[4] tt2[3] tt2[2] tt2[1] tt2[0] 0x00 0x2a cs2 release threshold w/r rt2 r8x2 rt2[6] rt2[5] rt2[4] rt2[3] rt2[2] rt2[1] rt2[0] 0x00 0x2b cs3 touch threshold w/r tt3 t8x3 tt3[6] tt3[5] tt3[4] tt3[3] tt3[2] tt3[1] tt3[0] 0x00 0x2c cs3 release threshold w/r rt3 r8x3 rt3[6] rt3[5] rt3[4] rt3[3] rt3[2] rt3[1] rt3[0] 0x00 0x2d cs4 touch threshold w/r tt4 t8x4 tt4[6] tt4[5] tt4[4] tt4[3] tt4[2] tt4[1] tt4[0] 0x00 0x2e cs4 release threshold w/r rt4 r8x4 rt4[6] rt4[5] rt4[4] rt4[3] rt4[2] rt4[1] rt4[0] 0x00 0x2f cs5 touch threshold w/r tt5 t8x5 tt5[6] tt5[5] tt5[4] tt5[3] tt5[2] tt5[1] tt5[0] 0x00 0x30 cs5 release threshold w/r rt5 r8x5 rt5[6] rt5[5] rt5[4] rt5[3] rt5[2] rt5[1] rt5[0] 0x00 0x31 cs6 touch threshold w/r tt6 t8x6 tt6[6] tt6[5] tt6[4] tt6[3] tt6[2] tt6[1] tt6[0] 0x00 0x32 cs6 release threshold w/r rt6 r8x6 rt6[6] rt6[5] rt6[4] rt6[3] rt6[2] rt6[1] rt6[0] 0x00 0x33 cs7 touch threshold w/r tt7 t8x7 tt7[6] tt7[5] tt7[4] tt7[3] tt7[2] tt7[1] tt7[0] 0x00 0x34 cs7 release threshold w/r rt7 r8x7 rt7[6] rt7[5] rt7[4] rt7[3] rt7[2] rt7[1] rt7[0] 0x00 0x35 cs8 touch threshold w/r tt8 t8x8 tt8[6] tt8[5] tt8[4] tt8[3] tt8[2] tt8[1] tt8[0] 0x00 0x36 cs8 release threshold w/r rt8 r8x8 rt8[6] rt8[5] rt8[4] rt8[3] rt8[2] rt8[1] rt8[0] 0x00 0x37 cs9 touch threshold w/r tt9 t8x9 tt9[6] tt9[5] tt9[4] tt9[3] tt9[2] tt9[1] tt9[0] 0x00 0x38 cs9 release threshold w/r rt9 r8x9 rt9[6] rt9[5] rt9[4] rt9[3] rt9[2] rt9[1] rt9[0] 0x00 0x39 cs10 touch threshold w/r tt10 t8x10 tt10[6] tt10[5] tt10[4] tt10[3] tt10[2] tt10[1] tt10[0] 0x00 0x3a cs10 release threshold w/r rt10 r8x10 rt10[6] rt10[5] rt10[4] rt10[3] rt10[2] rt10[1] rt10[0] 0x00 0x3b cs11 touch threshold w/r tt11 t8x11 tt11[6] tt11[5] tt11[4] tt11[3] tt11[2] tt11[1] tt11[0] 0x00 0x3c cs11 release threshold w/r rt11 r8x11 rt11[6] rt11[5] rt11[4] rt11[3] rt11[2] rt11[1] rt11[0] 0x00 0x3d cs12 touch threshold w/r tt12 t8x12 tt12[6] tt12[5] tt12[4] tt12[3] tt12[2] tt12[1] tt12[0] 0x00 0x3e cs12 release threshold w/r rt12 r8x12 rt12[6] rt12[5] rt12[4] rt12[3] rt12[2] rt12[1] rt12[0] 0x00 0x3f cs13 touch threshold w/r tt13 t8x13 tt13[6] tt13[5] tt13[4] tt13[3] tt13[2] tt13[1] tt13[0] 0x00 table 2. ak4160 register map (1)
[ak4160] ms1313-e-01 2011/11 - 18 - register description type symbol fields initial address d7 d6 d5 d4 d3 d2 d1 d0 value 0x40 cs13 release threshold w/r rt13 r8x13 rt13[6] rt13[5] rt13[4] rt13[3] rt13[2] rt13[1] rt13[0] 0x00 0x41 cs14 touch threshold w/r tt14 t8x14 tt14[6] tt14[5] tt14[4] tt14[3] tt14[2] tt14[1] tt14[0] 0x00 0x42 cs14 release threshold w/r rt14 r8x14 rt14[6] rt14[5] rt14[4] rt14[3] rt14[2] rt14[1] rt14[0] 0x00 0x43 cs15 touch threshold w/r tt15 t8x15 tt15[6] tt15[5] tt15[4] tt15[3] tt15[2] tt15[1] tt15[0] 0x00 0x44 cs15 release threshold w/r rt15 r8x15 rt15[6] rt15[5] rt15[4] rt15[3] rt15[2] rt15[1] rt15[0] 0x00 0x45 cs0 charge current w/r cc0 reserved reserved cc0[5] cc0[4] cc0[3 ] cc0[2] cc0[1] cc0[0] 0x00 0x46 cs1 charge current w/r cc1 reserved reserved cc1[5] cc1[4] cc1[3 ] cc1[2] cc1[1] cc1[0] 0x00 0x47 cs2 charge current w/r cc2 reserved reserved cc2[5] cc2[4] cc2[3 ] cc2[2] cc2[1] cc2[0] 0x00 0x48 cs3 charge current w/r cc3 reserved reserved cc3[5] cc3[4] cc3[3 ] cc3[2] cc3[1] cc3[0] 0x00 0x49 cs4 charge current w/r cc4 reserved reserved cc4[5] cc4[4] cc4[3 ] cc4[2] cc4[1] cc4[0] 0x00 0x4a cs5 charge current w/r cc5 reserved reserved cc5[5] cc5[4] cc5[3 ] cc5[2] cc5[1] cc5[0] 0x00 0x4b cs6 charge current w/r cc6 reserved reserved cc6[5] cc6[4] cc6[3 ] cc6[2] cc6[1] cc6[0] 0x00 0x4c cs7 charge current w/r cc7 reserved reserved cc7[5] cc7[4] cc7[3 ] cc7[2] cc7[1] cc7[0] 0x00 0x4d cs8 charge current w/r cc8 reserved reserved cc8[5] cc8[4] cc8[3 ] cc8[2] cc8[1] cc8[0] 0x00 0x4e cs9 charge current w/r cc9 reserved reserved cc9[5] cc9[4] cc9[3 ] cc9[2] cc9[1] cc9[0] 0x00 0x4f cs10 charge current w/r cc10 reserved reserved cc10[5] cc10[4] cc10[3] cc10[2] cc10[1] cc10[0] 0x00 0x50 cs11 charge current w/r cc11 reserved reserved cc11[5] cc11[4] cc11[3] cc11[2] cc11[1] cc11[0] 0x00 0x51 cs12 charge current w/r cc12 reserved reserved cc12[5] cc12[4] cc12[3] cc12[2] cc12[1] cc12[0] 0x00 0x52 cs13 charge current w/r cc13 reserved reserved cc13[5] cc13[4] cc13[3] cc13[2] cc13[1] cc13[0] 0x00 0x53 cs14 charge current w/r cc14 reserved reserved cc14[5] cc14[4] cc14[3] cc14[2] cc14[1] cc14[0] 0x00 0x54 cs15 charge current w/r cc15 reserved reserved cc15[5] cc15[4] cc15[3] cc15[2] cc15[1] cc15[0] 0x00 0x55 cs1/0 charge time w/r ct0 reserved ct1[2] ct1[1] ct1[0] reserved ct0[2] ct0[1] ct0[0] 0x00 0x56 cs3/2 charge time w/r ct2 reserved ct3[2] ct3[1] ct3[0] reserved ct2[2] ct2[1] ct2[0] 0x00 0x57 cs5/4 charge time w/r ct4 reserved ct5[2] ct5[1] ct5[0] reserved ct4[2] ct4[1] ct4[0] 0x00 0x58 cs7/6 charge time w/r ct6 reserved ct7[2] ct7[1] ct7[0] reserved ct6[2] ct6[1] ct6[0] 0x00 0x59 cs9/8 charge time w/r ct8 reserved ct9[2] ct9[1] ct9[0] reserved ct8[2] ct8[1] ct8[0] 0x00 0x5a cs11/10 charge time w/r ct10 reserved ct11[2] ct11[1] ct11[0] reserved ct10[2] ct10[1] ct10[0] 0x00 0x5b cs13/12 charge time w/r ct12 reserved ct13[2] ct13[1] ct13[0] reserved ct12[2] ct12[1] ct12[0] 0x00 0x5c cs15/14 charge time w/r ct14 reserved ct15[2] ct15[1] ct15[0] reserved ct14[2] ct14[1] ct14[0] 0x00 0x5d gpio data w/r gpdt gpdt[7] gpdt[6] gpdt[5 ] gpdt[4] gpdt[3] gpdt[2] gpdt[1] gpdt[0] 0x00 0x5e gpio enable w/r gpen gpen[7] gpen[6] gpen [5] gpen[4] gpen[3] gpen [2] gpen[1] gpen[0] 0x00 0x5f ac control w/r acc ace rce rcim cco vs[3] vs[2] vs[1] vs[0] 0x06 0x60 ac status r acs acs[15] acs[14] acs[13] acs[12] acs[11] acs[10] acs[9] acs[8] 0x00 0x61 r acs[7] acs[6] acs[5] acs[4] acs[3] acs[2] acs[1] acs[0] 0x00 0x62 multi touch inhibit w/r mti mti[15] mti[14] mti[13] mti[12] mti[11] mti[10] mti[9] mti[8] 0x00 0x63 w/r mti[7] mti[6] mti[5] mti[4] mti[3] mti[2] mti[1] mti[0] 0x00 0x64 irq control 0 w/r irqc0 gpen clrm high drv[1] drv[0] dstr pe pu 0x08 0x65 w/r drdy touch rel acf range gpin reserved lvl 0x00 0x66 irq mask 0 w/r irqm0 irqm[15] irqm[14] irqm[13] irqm[12] irqm[11] irqm[10] irqm[9] irqm[8] 0x00 0x67 w/r irqm[7] irqm[6] irqm[5] irqm [4] irqm[3] irqm[2] irqm[1] irqm[0] 0x00 0x68 irq control 1 w/r irqc1 gpen clrm high drv[1] drv[0] dstr pe pu 0x08 0x69 w/r drdy touch rel acf range gpin reserved lvl 0x00 0x6a irq mask 1 w/r irqm1 irqm[ 15] irqm[14] irqm[13] irqm[12] irqm[ 11] irqm[10] irqm[9] irqm[8] 0x00 0x6b w/r irqm[7] irqm[6] irqm[5] irqm [4] irqm[3] irqm[2] irqm[1] irqm[0] 0x00 0x6c irq control 2 w/r irqc2 gpen cl rm high drv[1] drv[0] dstr pe pu 0x08 0x6d w/r drdy touch rel acf range gpin reserved lvl 0x00 0x6e irq mask 2 w/r irqm2 irqm[ 15] irqm[14] irqm[13] irqm[12] irqm[ 11] irqm[10] irqm[9] irqm[8] 0x00 0x6f w/r irqm[7] irqm[6] irqm[5] irqm [4] irqm[3] irqm[2] irqm[1] irqm[0] 0x00 0x70 noise filter control w/r nfc nf2s[1] nf2s[0] nf1s[1] nf1s[0] rim[1] rim[0] lch rch 0x00 0x71 debounce control w/r deb debt[3] debt[2] debt[1] debt[0] debr[3] debr[2] debr[1] debr[0] 0x00 0x72 ef control w/r efc eup[5] eup[4] eup[3] eup[2] eup[1] eup[0] eur[1] eur[0] 0x00 0x73 w/r edp[5] edp[4] edp[3] edp[2] edp[1] edp[0] edr[1] edr[0] 0x00 0x74 sampling rate and channel control w/r scc tsr[2] tsr[1] tsr[0] nch[4] nch[3] nch[2] nch[1] nch[0] 0x00 0x75 reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x76 reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x77 reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x78 reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x79 reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x7a reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x7b reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x7c reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x7d reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 0x7e soft reset w/r srst srst[7] srst[6] srst [5] srst[4] srst[3] srst [2] srst[1] srst[0] 0x00 0x7f reserved - - reserved reserved reserved reserved reserved reserved reserved reserved 0x00 table 3. ak4160 register map (2)
[ak4160] ms1313-e-01 2011/11 - 19 - register description type symbol fields initial address d7 d6 d5 d4 d3 d2 d1 d0 value 0x80 cs0 reference data w/r ref0 reserved reserved reserved reserved reserved reserved ref0[9] ref0[8] 0x00 0x81 w/r ref0[7] ref0[6] ref0[5] ref0 [4] ref0[3] ref0[2] ref0[1] ref0[0] 0x00 0x82 cs1 reference data w/r ref1 reserved reserved reserved reserved reserved reserved ref1[9] ref1[8] 0x00 0x83 w/r ref1[7] ref1[6] ref1[5] ref1 [4] ref1[3] ref1[2] ref1[1] ref1[0] 0x00 0x84 cs2 reference data w/r ref2 reserved reserved reserved reserved reserved reserved ref2[9] ref2[8] 0x00 0x85 w/r ref2[7] ref2[6] ref2[5] ref2 [4] ref2[3] ref2[2] ref2[1] ref2[0] 0x00 0x86 cs3 reference data w/r ref3 reserved reserved reserved reserved reserved reserved ref3[9] ref3[8] 0x00 0x87 w/r ref3[7] ref3[6] ref3[5] ref3 [4] ref3[3] ref3[2] ref3[1] ref3[0] 0x00 0x88 cs4 reference data w/r ref4 reserved reserved reserved reserved reserved reserved ref4[9] ref4[8] 0x00 0x89 w/r ref4[7] ref4[6] ref4[5] ref4 [4] ref4[3] ref4[2] ref4[1] ref4[0] 0x00 0x8a cs5 reference data w/r ref5 reserved reserved reserved reserved reserved reserved ref5[9] ref5[8] 0x00 0x8b w/r ref5[7] ref5[6] ref5[5] ref5 [4] ref5[3] ref5[2] ref5[1] ref5[0] 0x00 0x8c cs6 reference data w/r ref6 reserved reserved reserved reserved reserved reserved ref6[9] ref6[8] 0x00 0x8d w/r ref6[7] ref6[6] ref6[5] ref6 [4] ref6[3] ref6[2] ref6[1] ref6[0] 0x00 0x8e cs7 reference data w/r ref7 reserved reserved reserved reserved reserved reserved ref7[9] ref7[8] 0x00 0x8f w/r ref7[7] ref7[6] ref7[5] ref7 [4] ref7[3] ref7[2] ref7[1] ref7[0] 0x00 0x90 cs8 reference data w/r ref8 reserved reserved reserved reserved reserved reserved ref8[9] ref8[8] 0x00 0x91 w/r ref8[7] ref8[6] ref8[5] ref8 [4] ref8[3] ref8[2] ref8[1] ref8[0] 0x00 0x92 cs9 reference data w/r ref9 reserved reserved reserved reserved reserved reserved ref9[9] ref9[8] 0x00 0x93 w/r ref9[7] ref9[6] ref9[5] ref9 [4] ref9[3] ref9[2] ref9[1] ref9[0] 0x00 0x94 cs10 reference data w/r ref10 reserved reserved reserved reserved reserved reserved ref10[9] ref10[8] 0x00 0x95 w/r ref10[7] ref10[6] ref10[5] ref 10[4] ref10[3] ref10[2] ref10[1] ref10[0] 0x00 0x96 cs11 reference data w/r ref11 reserved reserved reserved reserved reserved reserved ref11[9] ref11[8] 0x00 0x97 w/r ref11[7] ref11[6] ref11[5] ref 11[4] ref11[3] ref11[2] ref11[1] ref11[0] 0x00 0x98 cs12 reference data w/r ref12 reserved reserved reserved reserved reserved reserved ref12[9] ref12[8] 0x00 0x99 w/r ref12[7] ref12[6] ref12[5] ref 12[4] ref12[3] ref12[2] ref12[1] ref12[0] 0x00 0x9a cs13 reference data w/r ref13 reserved reserved reserved reserved reserved reserved ref13[9] ref13[8] 0x00 0x9b w/r ref13[7] ref13[6] ref13[5] ref 13[4] ref13[3] ref13[2] ref13[1] ref13[0] 0x00 0x9c cs14 reference data w/r ref14 reserved reserved reserved reserved reserved reserved ref14[9] ref14[8] 0x00 0x9d w/r ref14[7] ref14[6] ref14[5] ref 14[4] ref14[3] ref14[2] ref14[1] ref14[0] 0x00 0x9e cs15 reference data w/r ref15 reserved reserved reserved reserved reserved reserved ref15[9] ref15[8] 0x00 0x9f w/r ref15[7] ref15[6] ref15[5] ref 15[4] ref15[3] ref15[2] ref15[1] ref15[0] 0x00 table 4. ak4160 register map (3)
[ak4160] ms1313-e-01 2011/11 - 20 - register definition touch status register address 0x00 (r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 touch status ts[15] ts[14] ts[13] ts[12] ts[11] ts[10] ts[9] ts[8] address 0x01 (r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 touch status ts[7] ts[6] ts[5] ts[4] ts[3] ts[2] ts[1] ts[0] bits name description 15-0 ts touch status for each sense terminal 0: release 1: touch irq status register address 0x02 (r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 irq status drdy touch rel acf range gpin reserved reserved bits name description d7 drdy data ready interrupt the drdy bit is set to ?1? in the status of data ready. when the data ready interrupt is invalid, this bit is fix to ?0?. d6 touch touch interrupt the touch bit is set to ?1? in the status of touch transition. when touch interrupt is invalid, this bit is fix to ?0?. the sense terminal connected to the interrupt is selected by irqm register. (address 0x66~0x67, 0x6a~0x6b, 0x6e~0x6f) d5 rel release interrupt the rel bit is set to ?1? in the status of release transaction. when release interrupt is invalid, this bit is fix to ?0?. the sense terminal connected to the interrupt is selected by irqm register. (address 0x66~0x67, 0x6a~0x6b, 0x6e~0x6f) d4 acf automatic setting fail interrupt the acf bit is set to ?1?, when the measured value of the sense terminal is over the upper limit at the termination of automatic setting. when the automatic setting or the automatic setting fail interrupt is invalid, this bit is fix to ?0?. d3 range range over interrupt the range bit is set to ?1?, when the measured value of the sense terminal is over the upper limit. when the automatic resetting or the range over interrupt is invalid, the bit is fix to ?0?. d2 gpin gpio input interrupt the gpin bit is set to ?1? when a gp io input interrupt occurs. when the gpio input interrupt is invalid, the bit is fix to ?0?. d1-d0 reserved reserved when the irq bit (addr 0x03 irq2-0 bits) with permission of interrupt is cleared, th ese bits are also cleared.
[ak4160] ms1313-e-01 2011/11 - 21 - address 0x03 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 irq status iover reserved reserved reserved reserved irq2 irq1 irq0 bits name description d7 iover short detection of the rref pin the iover bit is set to ?1?, when the rref pin is shorted to vss in run mode. the ak4160 is changed from run mode to shutdown mode for the over current protection. the irq bit setting to the edge action is fix to the active state. when the iover bit is ?1?, run mode is invalid. when the i over bit is written ?1?, the iover bit or irq2-0 bits are cleared. d6-d3 reserved reserved: must write ?0? d2-d0 irq2-0 irq status the edge action case the irq bits are set to ?1?, when an in terrupt occurs. there are 2ways to clear these bits. it is selected by clrm bit in the irqcn register. clrm bit = ?0?: when the lower byte of the irq status register is read. clrm bit = ?1?: when the related bit (irq2-0 bits) is written ?1?, the bit is cleared the level action case the irq bits are set to the input level of irqn2-0 terminals. reading or writing ?1? to the irq bits is invalid. the gpio function the irq bits are set to the level of irqn2-0 terminals. reading or writing ?1? to the irq bits is invalid.
[ak4160] ms1313-e-01 2011/11 - 22 - gpio input data register address 0x04 (r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 gpio input data gpin[7] gpin[6] gpin[5] gpin[4] gpin[3] gpin[2] gpin[1] gpin[0] bits name description d7-d0 gpin the level output of gpio the reading value changes at each setting of gpio. ( table 5 ) gpen ( note 23 ) direction ( note 24 ) debounce ( note 25 ) src1-0 bits ( note 26 ) the value that returned from gpio 0 - - - 0 invalid - terminal level input valid - debounced level - 00 terminal level 1 output - 01, 10, 11 output enable note 23. this is the setting value at the address 0x5e. note 24. this is set by dir bit at the address 0x35~0x44. note 25. this is set by deb1[3:0] bits and deb0[3:0] bits at address 0x35~0x44. note 26. this is set by src1-0 bits at address 0x32~0x44. table 5. gpio register value
[ak4160] ms1313-e-01 2011/11 - 23 - capacitor sense data register (csdn: n=0~15) address 0x05/0x07/.../0x23 (r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 csn data register csdn[15] csdn[14] csdn[13] csdn[12] csdn[11] csdn[10] csdn[9] csdn[8] address 0x06/0x08/?/0x24 (r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 csn data register csdn[7] csdn[6] csdn[5] csdn[4] csdn[3] csdn[2] csdn[1] csdn[0] bits name description 15-0 csdn measurement data of each sense terminal the last measurement data is kept when the operating state is changed from run-mode to shutdown-mode. afterwards, the measurement data is updated in run-mode whenever the data is settled. cs address cs address cs0 0x05 - 0x06 cs8 0x15 - 0x16 cs1 0x07 - 0x08 cs9 0x17 - 0x18 cs2 0x09 - 0x0a cs10 0x19 - 0x1a cs3 0x0b - 0x0c cs11 0x1b - 0x1c cs4 0x0d - 0x0e cs12 0x1d - 0x1e cs5 0x0f - 0x10 cs13 0x1f - 0x20 cs6 0x11 - 0x12 cs14 0x21 - 0x22 cs7 0x13 - 0x14 cs15 0x23 - 0x24 table 6. address to each cs pins
[ak4160] ms1313-e-01 2011/11 - 24 - threshold register (thn: n=0~15) address 0x25/0x27/?/0x43 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 csn touch threshold t8xn ttn[6] ttn[5] ttn[4] ttn[3] ttn[2] ttn[1] ttn[0] address 0x26/0x28/?/0x44 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 csn release threshold r8xn rtn[6] rtn[5] rtn[4] rtn[3] rtn[2] rtn[1] rtn[0] bits name description d7 t8xn the touch threshold of the terminal csn is increased by a factor of eight. d6-d0 ttn the touch threshold of the terminal csn is set. t8xn=0: the threshold is 0~127 (step 1) t8xn=1: the threshold is 0~1016 (step 8) bits name description d7 r8xn the release threshold of the terminal csn is increased by a factor of eight. d6-d0 rtn the release threshold of the terminal csn is set. r8xn=0: the threshold is 0~127 (step 1) r8xn=1: the threshold is 0~1016 (step 8) the threshold register should not be updated in run-mode. when the sense terminal is set to gpio, the threshold re gister becomes a gpio control register gpcn (n=0~7). address cs gpio 0x25 ? 0x26 cs0 threshold register - 0x27 ? 0x28 cs1 threshold register - 0x29 ? 0x2a cs2 threshold register - 0x2b ? 0x2c cs3 threshold register - 0x2d ? 0x2e cs4 threshold register - 0x2f ? 0x30 cs5 threshold register - 0x31 ? 0x32 cs6 threshold register - 0x33 ? 0x34 cs7 threshold register - 0x35 ? 0x36 cs8 threshold register gpio7 control register 0x37 ? 0x38 cs9 threshold register gpio6 control register 0x39 ? 0x3a cs10 threshold register gpio5 control register 0x3b ? 0x3c cs11 threshold register gpio4 control register 0x3d ? 0x3e cs12 threshold register gpio3 control register 0x3f ? 0x40 cs13 threshold register gpio2 control register 0x41 ? 0x42 cs14 threshold register gpio1 control register 0x43 ? 0x44 cs15 threshold register gpio0 control register table 7. cs threshold register and gpio control register gpio control regist er (gpcn: n=0~7) cs8~cs15 can be used as gpio by setting gpio enable register (addr 0x5e). in this case, the threshold register works as the gpio control register. the bit allocation of the gpio contro l register at the input setting (dir bit = ?0?) is different from the allocation at the output setting (dir bit = ?1?).
[ak4160] ms1313-e-01 2011/11 - 25 - gpio input control register address 0x35/0x37/?/0x43 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 gpio input control dir reserved reserved reserved irqc[1] irqc[0] pe pu address 0x36/0x38/?/0x44 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 gpio input control deb1[3] deb1[2] deb1[1] deb1[0] deb0[3] deb0[2] deb0[1] deb0[0] bits name description d7 dir this bit should be set to ?0? at the input setting of gpio. d6-d4 reserved reserved: this bit should be written by ?0?, when writing. d3-d2 irqc gpio interrupt setting 00: no interrupt 01: interrupt on a rising edge 10: interrupt on a falling edge 11: interrupt on both edges d1 pe pull-up, pull-down enable 0: invalid 1: valid. the direction is fixed by pu bit. d0 pu pull-up / pull-down selector 0: pull-down 1: pull-up bits name description d7-d4 deb1 debounce setting at rising edge when ?1? is detected ?2 x 2 deb1? times in a row with 31.25us of the sampling frequency, the result of input is set to ?1?. ( table 8 ) however, when deb1[3:0] bits = ?0?, the result is updated by detecting ?1? one time. d3-d0 deb0 debounce setting at falling edge when ?1? is detected ?2 x 2 deb0? times in a row with 31.25us of the sampling frequency, the result of input is set to ?0?. ( table 8 ) however, when deb0[3:0] bits = ?0?, the result is updated by detecting ?1? one time. deb0, deb1 consecutive number consecutive time (ms) deb0, deb1 consecutive number consecutive time (ms) 0000 1 - 1000 512 16 0001 4 0.125 1001 1024 32 0010 8 0.25 1010 2048 64 0011 16 0.5 1011 4096 128 0100 32 1 1100 8192 256 0101 64 2 1101 16384 512 0110 128 4 1110 32768 1024 0111 256 8 1111 32768 1024 table 8. debounce setting refer to table 7 for the correspondence of the regi ster address and the gpio pin.
[ak4160] ms1313-e-01 2011/11 - 26 - gpio output control register address 0x35/0x37/?/0x43 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 gpio output control dir rel src[1] src[0] drv[1] drv[0] inv dstr address 0x36/0x38/?/0x44 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 gpio output control pwm prd[1] prd[0] duty[4] duty[3] duty[2] duty[1] duty[0] bits name description d7 dir this bit should be set to ?1? at the output setting of gpio. d6 rel the output setting (src1-0 bits = ?01?, ?10?, ?11?) 0: touch status 1: release status d5-d4 src the selection of output data 00: the value set by gpdt register (addr 0x5d) is output. 01: the status value set by rel bit is output. 10: the status value set by rel bit is output in the toggle. (initial value 0) 11: the status value set by rel bit is output in the toggle. (initial value 1) when the touch status (release status) is selected as output data, the terminal gpion outputs the status of terminal csn (n=0~7). touch status is recognized as ?0? at shutdown mode. the output value is initialized by writing ?0? to corresponding gpdt register (addr 0x5d) when src1-0 bits = ?01?, ?10?, ?11?. 01: the output value is initialized by ?0?. 10: the output value is initialized by ?0?. 11: the output value is initialized by ?1?. d3-d2 drv output driver setting 00: cmos output 01: low side output: when output is ?h?, hi-z (open drain) 10: high side output: when output is ?l?, hi-z (open drain) 11: cmos output (same as 00 setting) d1 inv the output level is reversed. d0 dstr the driving ability of the gpio output driver is set. 0: 1/3 drive 1: full drive bits name description d7 pwm pwm output enable d6-d5 prd cycle of the pwm output is set. 00: 125hz 01: 250hz 10: 500hz 11: 1000hz d4-d0 duty duty of the pwm output is set. duty=(duty + 1) / 32: 1/32 ~ 32/32 refer to table 7 for the correspondence of the regi ster address and the gpio pin.
[ak4160] ms1313-e-01 2011/11 - 27 - charge current register (ccn: n=0~15) address 0x45-0x54 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 charge current reserved reserved ccn[5] ccn[4] ccn[3] ccn[2] ccn[1] ccn[0] bits name description d7-d6 reserved reserved: this bit should be written ?0?. d5-d0 ccn the charge current from the terminal csn is set. 0.556 x ccn x vdd [ua] when automatic setting is valid (addr 0x5f ace bit = ?1?), these bits are updated after the setting is completed. th is value may not be correct during the automatic setting. these bits can not be changed by the serial i/f in run-mode. charge time register (ctn: n= 0, 2, 4, 6, 8, 10, 12, 14) address 0x55-0x5c (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 charge time reserved ctn+1[2] ctn+1[1] ctn+1[0] reserved ctn[2] ctn[1] ctn[0] bits name description d7,d3 reserved reserved: this bit should be written ?0?. d6-d4 d2-d0 ctn+1 ctn the charge time at the terminal csn is set. 0.25us~32us = 0.25us x 2 ctn when automatic setting is valid (addr 0x5f ace bit = ?1?), these bits are updated after the setting is completed. th is value may not be correct during the automatic setting. these bits can not be changed by the serial i/f in run-mode. gpio date register (gpdt) address 0x5d (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 gpio data register gpdt[7] gpdt[6] gpdt[5] gpdt[4] gpdt[3] gpdt[2] gpdt[1] gpdt[0] bits name description d7-d0 gpdt gpio output data setting when the touch status is output (src1-0 bits = ?01?, ?10?, ?11?), the output is valid according to gpdt7-0 bits = ?1?. gpio enable register (gpen) address 0x5e (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 gpio enable register gpen[7] gpen[6] gpen[5] gpen[4] gpen[3] gpen[2] gpen[1] gpen[0] bits name description d7-d0 gpen gpio enable exclusive control is provided for the sense terminal select (scc register nch bit). when a pin has already been selected as gpio, the sense terminal selection is invalid.
[ak4160] ms1313-e-01 2011/11 - 28 - auto calibration control register (acc) address 0x5f (w/r) default 0x06 description d7 d6 d5 d4 d3 d2 d1 d0 auto calibration control ace rce rim cco vs[3] vs[2] vs[1] vs[0] bits name description d7 ace the automatic setting of the charge current and the charge time is enabled. the charge current and the charge time is set automatically at the first measurement, and each register is upda ted. when the function of automatic setting is valid, the vs3-0 bits must be configured. d6 rce the automatic reconfiguration is enabled. the reconfiguration is operated automatically when the measurement data is over the upper limit. d5 rim reference value setting of the reconfiguration 0: the first measurement value is set as the initial value of the reference after reconfiguration. 1: 31/32 of the first measurement value is set as the initial value of the reference after reconfiguration. d4 cco automatic setting of the charge current only the charge time is not automatically configured, and it is set to the value of ct register. only charge current is automatically set. d3-d0 vs the lowest operation voltage setting the best charge current and charge time in the power supply voltage selected with these bits are automatically configured. at the power supply voltage selected by these bits, the charge current and the charge time are auto matically optimized. the initial value is ?0110?. (1.71v ~1.9v) these bits can not be changed by the serial i/f in run-mode. vs[3:0] lowest operation voltage upper limit voltage of sense terminals setting voltage 0000-0101 reserved reserved reserved 0110 vdd 1.71v 1.50v 1.35v 0111 vdd 1.9v 1.70v 1.53v 1000 vdd 2.1v 1.90v 1.71v 1001 vdd 2.3v 2.10v 1.89v 1010 vdd 2.5v 2.30v 2.07v 1011 vdd 2.7v 2.50v 2.25v 1100 vdd 2.9v 2.70v 2.43v 1101 vdd 3.1v 2.90v 2.61v 1110 vdd 3.3v 3.10v 2.79v 1111 vdd 3.5v 3.30v 2.97v table 9. reference value of automatic setting
[ak4160] ms1313-e-01 2011/11 - 29 - auto calibration status register (acs) address 0x60 (r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 auto calibration status acs[15] acs[14] acs[13] acs[12] acs[11] acs[10] acs[9] acs[8] address 0x61 (r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 auto calibration status acs[7] acs[6] acs[5] acs[4] acs[3] acs[2] acs[1] acs[0] bits name description 15-0 acs automatic setting status when the automatic setting is failed or the measurement data is over the upper limit, these bits are set. when the reco nfiguration is valid (addr 0x5e rce bit = ?1?), these bits are cleared by the successful reconfiguration. multi touch inhibit register (mti) address 0x62 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 multi touch inhibit mti[15] mti[14] mti[13] mti[12] mti[11] mti[10] mti[9] mti[8] address 0x63 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 multi touch inhibit mti[7] mti[6] mti[5] mti[4] mti[3] mti[2] mti[1] mti[0] bits name description 15-0 mti prohibition of multi touch sense terminals to prohibit the multi touch function are selected by these bits. the operational mode without the multi touch function is controlled by rch bit and lch bit of address ?0x70?.
[ak4160] ms1313-e-01 2011/11 - 30 - irq control register (irqcn: n=0~2) these are the control registers of the irq pins. when the ir q pins are used as gpio, the bit allocation is different. irq interrupt register (when gpen bit = ?0?) address 0x64/0x68/0x6c (w/r) default 0x08 description d7 d6 d5 d4 d3 d2 d1 d0 irq interrupt gpen clrm high drv[1] drv[0] dstr pe pu address 0x65/0x69/0x6d (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 irq interrupt drdy touch rel acf range gpin reserved tsl bits name description d7 gpen gpio enable this bit should be set to ?0? in the irq operation. d6 clrm clearance setting of irq status (addr 0x03 irq2-0 bits) 0: read clear of irq status 1: write clear of irq status (clear to write ?1? to irq2-0 bits) irq status is cleared in the edge operatio n. the status is not changed in the level operation. d5 high polarity selection of irq pins 0: active low 1: active high] irq pins are always non-active in the shutdown mode. d4-d3 drv output driver setting 00: cmos output 01: low side output: when output is ?h?, hi-z (open drain) 10: high side output: when output is ?l?, hi-z (open drain) 11: cmos output (same as 00 setting) d2 dstr the driving ability of the gpio output driver is set. 0: 1/3 drive 1: full drive d1 pe pull-up, pull-down enable 0: invalid 1: valid. the direction is fixed by pu bit. d0 pu pull-up / pull-down selector 0: pull-down 1: pull-up
[ak4160] ms1313-e-01 2011/11 - 31 - bits name description d7 drdy permission of data ready interrupt this interrupt is generated at the end of a measurement. the measurement value should be read from csdn register (addr 0x05-0x24). the interrupt interval is ?sampling rate x number of sample?. the ?number of sample? is set by nf2s bits in addr 0x70. d6 touch permission of touch interrupt the intended terminal can be config ured by irq mask register (addr 0x66-0x67, 0x6a-0x6b, 0x6e-0x6f). d5 rel permission of release interrupt the intended terminal can be config ured by irq mask register (addr 0x66-0x67, 0x6a-0x6b, 0x6e-0x6f). d4 acf permission of automatic configuration fail interrupt when the measurement value on automatic configuration is out of the stipulated range, this interrupt is generated. d3 range permission of upper limit over interrupt when the measurement value is over the upper limit in a measurement operation, this interrupt is generated. d2 gpin permission of gpio input interrupt when the interrupt function is configur ed by gpio control registers (addr 0x35/0x37/?/0x43 irqc bit),this interrupt is generated by the factor occurrence. d1 reserved reserved: this bit should be written ?0?. d0 tsl level output operational mode selection of touch status 0: edge operation the irq pin responds to the edge for the in terrupt factor selected by drdy bit, touch bit, rel bit, acf bit, range b it, and gpin bit. the clearance setting, polarity setting, driver setting, and etc. are configured by addr 0x65/0x69/0x6d. 1: level operation touch function or release function is selected by touch bit and rel bit. the intended terminal can be configured by irq mask register (addr 0x66-0x67, 0x6a-0x6b, 0x6e-0x6f). the other interrupt factor cannot be selected. the polarity setting, driver setting, and etc. are configured by addr 0x65/0x69/0x6d. the status cannot be cleared unlike the edge operation. the irq status (irq2-0 bit of addr 0x03) returns the input level of the irq pin.
[ak4160] ms1313-e-01 2011/11 - 32 - irq gpio register (gpen bit = ?1?) address 0x64/0x68/0x6c (w/r) default 0x08 description d7 d6 d5 d4 d3 d2 d1 d0 irq gpio gpen dir dat drv[1] drv[0] dstr pe pu address 0x65/0x69/0x6d (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 irq gpio reserved reserved reserved reserved reserved reserved reserved reserved bits name description d7 gpen gpio enable this bit should be set to ?1? at the gpio operation. d6 dir gpio input/output selection 0: input configuration 1: output configuration d5 dat gpio output data when gpio is output configuration, the output data is setting by this bit. d4-d3 drv output driver setting 00: cmos output 01: low side output: when output is ?h?, hi-z (open drain) 10: high side output: when output is ?l?, hi-z (open drain) 11: cmos output (same as 00 setting) d2 dstr the driving ability of the gpio output driver is set. 0: 1/3 drive 1: full drive d1 pe pull-up, pull-down enable 0: invalid 1: valid. the direction is fixed by pu bit. d0 pu pull-up / pull-down selector 0: pull-down 1: pull-up bits name description d7-d0 reserved reserved: this bit should be written ?0?.
[ak4160] ms1313-e-01 2011/11 - 33 - irq mask register (irqmn: n=0~2) address 0x66/0x6a/0x6e (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 irq mask irqm[15] irqm[14] irqm[13] irqm[12] irqm[11] irqm[10] irqm[9] irqm[8] address 0x67/0x6b/0x6f (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 irq mask irqm[7] irqm[6] irqm[5] irqm[4] irqm[3] irqm[2] irqm[1] irqm[0] bits name description 15-0 irqm intended channel setting of touch/release interrupt 0: no target of interrupt 1: target of interrupt noise filter control register (nfc) address 0x70 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 noise filter control nf2s[1] nf2s[0] nf1s[1] nf1s[0] rim[1] rim[0] lch rch bits name description d7-d6 nf2s number of samples at the noise filter (the second filter) 00: 4 samples 01: 6 samples 10: 10 samples 11: 18 samples d5-d4 nf1s number of samples at the noise filter (the first filter) 00: 4 samples 01: 6 samples 10: 10 samples 11: 18 samples d3-d2 rim initial reference setting selection 00: user setting (reference value set by addr 0x80-0x9f refn bits) 01: first measurement value as a reference 10: 31/32 of first measurement value as a reference 11: 30/32 of first measurement value as a reference d1 lch priority setting of sense terminals without multi touch function 0: the sense terminal to touch most strongly is selected. 1: the sense terminal of the youngest number is selected. d0 rch release operation setting of sense terminals without multi touch function 0: the next touch judgment is not executed until all the sense terminals are released once. 1: when the sense terminal that is judged as touched is released, the next touch judgment is executed. these bits can not be changed by the serial i/f in run-mode.
[ak4160] ms1313-e-01 2011/11 - 34 - debounce control register (deb) address 0x71 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 debounce control debt[3] debt[2] debt[1] debt[0] d ebr[3] debr[2] debr[1] debr[0] bits name description d7-d4 debt debounce count setting of the touch judgment when the touch recognition is consecu tive, it is judged as ?touched?. the consecutive time is set by these bits. d3-d0 debr debounce count setting of the release judgment when the release recognition is consecutive, it is judged as ?released?. the consecutive time is set by these bits. the condition to use both the multi touch prohibition function and the debounce function: debt debr these bits can not be changed by the serial i/f in run-mode. environment filter control register (efc) address 0x72 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 environment filter control eup[5] eup[4] eup[3] eup[2] eup[1] eup[0] eur[1] eur[0] address 0x73 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 environment filter control edp[5] edp[4] edp[3] edp[2] edp[1] edp[0] edr[1] edr[0] bits name description d7-d2 eup operation interval of the environmental correction filter (measurement > reference) operation at each ?output rate (1+eup)?, (eup = 0~63) output rate = sampling rate nf2s (addr 0x70) d1-d0 eur operation coefficient of the environmental correction filter (measurement > reference) reference = reference ? (reference ? meas urement) / (2^(eur+1)), (eur = 0~3) this bits can not be changed by the serial i/f in run-mode. bits name description d7-d2 edp operation interval of the environmental correction filter (measurement < reference) operation at each ?output rate (1+edp)?, (edp = 0~63) output rate = sampling rate nf2s (addr 0x70) d1-d0 edr operation coefficient of the environmental correction filter (measurement < reference) reference = reference ? (reference ? meas urement) / (2^(edr+1)), (edr = 0~3) these bits can not be changed by the serial i/f in run-mode.
[ak4160] ms1313-e-01 2011/11 - 35 - sampling rate & sense channel control register (scc) address 0x74 (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 sampling rate & sense channel control tsr[2] tsr[1] tsr[0] nch[4] nch[3] nch[2] nch[1] nch[0] bits name description d7-d5 tsr measurement sampling rate setting fs = 4ms x 2 tsr (4ms~512ms) d4-d0 nch measurement channel setting exclusive control is provided for gpio enable function (addr 0x5e). when a pin has already been selected as gpio, the sense terminal selection is invalid. refer to table 10 for the selection setting. tsr can be changed in run mode. nch sense setting terminal nch sense setting terminal 00000 no selection (shutdown mode) 01001 cs0 ~ cs8 00001 cs0 01010 cs0 ~ cs9 00010 cs0 ~ cs1 01011 cs0 ~ cs10 00011 cs0 ~ cs2 01100 cs0 ~ cs11 00100 cs0 ~ cs3 01101 cs0 ~ cs12 00101 cs0 ~ cs4 01110 cs0 ~ cs13 00110 cs0 ~ cs5 01111 cs0 ~ cs14 00111 cs0 ~ cs6 01000 cs0 ~ cs7 10000 - 11111 cs0 ~ cs15 table 10. sense setting terminal
[ak4160] ms1313-e-01 2011/11 - 36 - soft reset register (srst) address 0x7e (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 soft reset srst[7] srst[6] srst[5] srst[4] srst[3] srst[2] srst[1] srst[0] bits name description d7-d0 srst when ?srst=0x55? is written, reset is generated. all registers become the initial values. this register is read as ?0x00?. reference data register (refn: n=0~15) address 0x80/0x82/?/0x9e (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 reference data reserved reserved reserved reserved reserved reserved refn[9] refn[8] address 0x81/0x83/?/0x9f (w/r) default 0x00 description d7 d6 d5 d4 d3 d2 d1 d0 reference data refn[7] refn[6] refn[5] refn[4] refn[3] refn[2] refn[1] refn[0] bits name description 15-10 reserved reserved: this bit should be written ?0?. 9-0 refn reference value for each sense terminal
[ak4160] ms1313-e-01 2011/11 - 37 - system design figure 18 and figure 19 show the system connection diagram for the ak4160. an evaluation board [AKD4160] demonstrates the optimum layout, power supply arrangements and measurement results. <16ch touch switch> ak4160 cs0 ~ cs15 touch switch 7 8 9 x 4 5 6 / 1 2 3 + 0 = ac ? vdd scl rref vreg irq2n irq1n rstn irq0n sda ad0 ad1 vss 100kohm 47nf up figure 18. typical connection diagram for 16ch touch switch <8ch touch switch & 8ch led display > ak4160 cs0 ~ cs7 touch switch vdd scl rref vreg irq2n irq1n rstn irq0n sda ad0 ad1 vss 100kohm 47nf up led display gpio0 ~ gpio7 vol vo l ch ch on men u mute ext off up up dn dn figure 19. typical connection diagram for 8ch touch switch & 8ch led display note: - these figures are the connection diagram when the ad 0 pin = ?l? and the ad1 pin = ?l?. in case of the ad0 pin = ?h? or the ad1 pin = ?h?, their pin must be connected to vdd. - vss of the ak4160 should be distributed separately from the ground of external controllers. - all digital input pins (scl, sda, ad0, ad 1, rstn pins) must not be left floating.
[ak4160] ms1313-e-01 2011/11 - 38 - package 4.000.05 4.000.05 a b 0.180.05 22 1 7 8 14 15 21 28 0.400.05 c 0.40 ref 2.300.10 2.300.10 0.08 c 0.05max 0.750.05 c0.3 m 0.07 c a b 28pin qfn (unit: mm) top view bottom view note: the thermal die pad must be open or connected to the ground. package & lead frame material package molding compou nd: epoxy resin, halogen (br, cl) free lead frame material: cu alloy lead frame surface treatment: solder plate
[ak4160] ms1313-e-01 2011/11 - 39 - marking 4160 x xx x date code: xxxx (4 digits) pin #1 indication
[ak4160] ms1313-e-01 2011/11 - 40 - date (y/m/d) revision reason page contents 11/07/25 00 first edition specification addition 6 dc characteristics pull-up current were added: 5ua (min), 200ua (max) pull-down current were added: -200ua (min), -5ua (max) 11/11/24 01 error correction 34 register definition operation interval expression (eup) was changed: output rate/(1+eup) output rate(1+eup) operation interval expression (edp) was changed: output rate/(1+edp) output rate(1+edp) important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporatio n of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. revision history

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